This invention is in the field of signal limiters, and relates more specifically to current limiters having programmable upper and lower current limits, and an intermediate linear range.
Several prior art approaches are available for signal limiting. One approach is adapted to a differential transistor pair amplifier and is shown in FIG. 1. The differential transistor amplifier consists of emitter coupled transistors 14 and 16, bias current source 18, and load resistors 10 and 12. The amplifier is coupled between V.sub.CC and V.sub.EE, two sources of supply voltage. The amplifier is driven by a differential input voltage (+V.sub.IN, -V.sub.IN) and the output voltage is developed across the collectors of transistors 14 and 16. The limiting circuitry consists of diode strings 20, 22 and 24, and 26, 28, and 30. Due to the clamping action of the diodes in the limiting circuitry, the maximum differential output voltage of the amplifier is limited to three diode drops above the quiescent output voltage whereas the minimum differential output voltage is limited to three diode drops below the quiescent output voltage.
This approach has several disadvantages. The amount of signal limiting is constrained to discrete values determined by the number of diodes used in the diode strings. Further, the clamping action is not sharp and precise, but determined by the diode voltage and current characteristics which produce a soft, poorly determined clamping point. The clamping point, since it is determined by the diode characteristics is also sensitive to changes in temperature. Also, this prior art signal limiting technique is only useful for voltage signal limiting, and is not suited to current signal limiting. Finally, this approach cannot be directly adapted to single ended amplifiers.
An improved prior art signal limiting circuit is shown in FIG. 2. The differential amplifier is identical to the one shown in FIG. 1, with the exception of the signal limiting circuit. The signal limiting circuit consists of diodes 32 and 34, and diodes 36 and 38. The diodes are coupled to the collectors of transistors 14 and 16, and are also coupled to reference voltages V.sub.1 and V.sub.2. This signal limiting circuit limits the voltage at the collectors of transistors 14 and 16 to a maximum of one diode drop above V.sub.2 and to a minimum of one diode drop below V.sub.1. This technique is not limited to discrete amounts of signal limiting, since the reference voltages V.sub.1 and V.sub.2 may be adjusted to any voltage which is desired. This technique may also be adapted to single ended amplifiers. However, all the other disadvantages of the limiting circuit shown in FIG. 1 remain.
A prior art current limiting approach is shown in FIG. 3. This approach is used mainly in output stages wherein transistor 40 is an output signal device used to deliver output load current. As the output current increases, a voltage is developed across resistor 44. As this voltage increases transistor 42 begins to conduct, steering base current away from transistor 40 and thus limiting the output current of transistor 40. Although this approach is used for current limiting, it suffers from many of the same disadvantages of the previous two prior art techniques. The clamping point occurs when the voltage across resistor 44 is sufficient to enable transistor 42 to conduct. This clamping point is not precisely defined due to the soft conduction characteristics of the emitter base junction of transistor 42. Further, the input and output currents are related by the beta of transistor 40 which adds further imprecision and temperature sensitivity to the clamping point of the signal limiting circuitry.
One final prior art current limiting approach is shown in FIG. 4 which does not have the disadvantages associated with the soft conduction characteristics of a diode. The circuit consists of a reference current 46 which is labeled I.sub.REF, an input NPN transistor 52, an output PNP transistor 50, and a diode 48. For an input current I.sub.IN of zero, a maximum current output current is developed equal to the reference current I.sub.REF. The polarity of the emitter base junction of transistor 50 turns diode 48 off. As I.sub.IN increases slightly, a corresponding decrease in the output current will be developed. The input current and output current are thus linearly related, although the polarities are inverted. The linear region continues until the input current is equal to or exceeds the reference current. In this limiting mode, the output current of transistor 50 is zero, with the current demands of transistor 52 being provided by the reference current I.sub.REF and the excess by the reference voltage V.sub.REF, through diode 48. This approach has several disadvantages. The inversion between the input current and the output current may not be desirable. Also, the minimum input current limit is fixed at zero. Finally, the introduction of the PNP transistor adversely affects the frequency response of the circuit when fabricated with readily available integrated circuit processes.
Therefore, what is desired is a signal current limiting circuit which has all NPN transistor circuitry for maximum frequency response, a precisely defined minimum input current limit as well as a precisely defined maximum input current limit, linear operation when not in a current limit mode, equal polarity input and output current, and adaptability to single ended or differential amplifiers.